While in steady-state operation, a defect-free CMOS circuit draws a minimal, but acceptable, amount of leakage current. In contrast, a defective CMOS chip produces a large quiescent current by virtue of a direct current path from the power supply to ground. The existence of such a path may lead to a reliability and performance degradation of the device. There are several methods, including current supply monitoring, for determining whether an integrated circuit is defect free.
The technique of monitoring supply current, commonly referred to as IDDQ or quiescent-current testing, has been established as an effective technique for assuring the quality and reliability of CMOS circuits. In an IDDQ test, a set of input vectors is applied to a chip in order to detect whether the circuit, in response to the stimuli, produces an unacceptably large quiescent current. Due to the size and complexity of many circuits, a small subset of all possible vectors is usually preselected for use in an IDDQ test. Simulation is one of the techniques used for preselecting a reduced set of test vectors.
In circuit simulation, using a conventional circuit simulator such as Verilog-XL or Quickhdl, a set of input vectors is applied to a model of the circuit under test. The steady-state response of each simulated circuit node is monitored and recorded. If in response to a simulated input vector, none of the simulated circuit nodes settle on a high-current state the vector is identified as a revealing test vector. This is because any quiescent current produced by an actual circuit in response to the identified test vector must be attributed to a circuit defect rather than to a high-current state. Simulated test vectors that yield high-current states are ignored, since they are not likely to distinguish an acceptable circuit from one that is defective.
As the size and complexity of CMOS circuits continue to increase, the size of the simulation results files follow suit. Also, the expense and time required to identify the subsets of test vectors using the above technique increases. Thus there is a need for a means to quickly and cheaply identify the smallest sets of test vectors that adequately test the circuits in question.